This invention relates to a semiconductor memory device, more particularly to a dynamic type random access memory device capable of partial activation of a memory cell array that is divided into a plurality of blocks.
Recently the partial activation technique in RAM devices has been developed in which a memory cell array is divided into a plurality of memory cell array blocks and selectively activated to output read data andr to receive write data. According to this technique, only one or a few memory cell array blocks are activated to connect certain memory cells selected in accordance with address signals to bit lines and other memory cell array blocks are maintained in deactivated states in which the bit lines remain in precharged state. Therefore, in the device performing the partial activation operation, the current consumption owing charging and discharging the bit lines, that is, voltage inversions on the bit lines, which do not correspond to the selected memory cells is decreased. In particular, since the current consumption of the RAM device is mainly caused by the voltage inversion on the bit lines, the total current consumption of the RAM device is effectively decreased.
This type of prior art device is explained with reference to FIG. 11 and 12. As shown in FIG. 11, the RAM device comprises n block areas B1 . . . Bn, a timing controller TC for receiving control signals RAS, CAS, an address buffer AB1 for receiving a row address signal AddR and a block address signal AddB which is associated with a refresh counter RC for outputting the row address signal AddR and the block address signal AddB to the address buffer AB1 in order to refresh certain memory cell array blocks CAB1, CABn, an address buff for AB2 for receiving a column address signal AddC, and a block selector for outputting block selection signals SL1 . . . SLn. The block area B1 has a memory cell array block CAB1 including the memory cells MC111 each associated with a word line WL11 and the bit line pair BL111a, BL111b, a sense amplifier circuit SA1 associated with a sense amplifier driver SAD1 which outputs a high level signal to activate the sense amplifier circuit SA1 according to the high level state of the block selection signal SL1, a column selector CS1 associated with a column decoder CD1 which is activated according to the high level state of the signal SL1, a row decoder RD1 associated with a word driver WD1 which outputs a high level signal to activate the row decoder RD1 according to the high level state of the signal SL1, an x-predecoder PD1 which prodecodes the row address signal AddR1 according to the high level state of the signal SL1, a bit line balance and precharge circuit BB1 associated with a bit line balance and precharge circuit driver BBD1 which outputs a high level signal to activate the bit line balance and precharge circuit BB1 according to the high level state of the signal SL1. Each of the other block areas Bn has equivalent elements respectively. The sense amplifier circuits SA1 . . . SAn are connected to a common data line DL1a which is connected to a read amplifier RA9 associated with an output buffer OB9, and to a write amplifier WA9 associated with an input buffer IB9.
The operation of this device is as follows. To perform a read operation, according to FIG. 12, the row and block address signals AddR and AddB are preliminary changed and, at time t11, the external input row address strobe signal RAS goes to the low level. Then the address latch signal AL11 being output from the timing controller TC to the address buffer AB1 turns to the high level and enables the address buffer AB1 to latch the address signals AddR, AddB. The address enable signal AE11 also turns to the high level subsequently and enables to the address buffer AB1 to output the row address signal AddR1 and the block address signal AddB1. In this state, the block selection signals SL1 . . . SLn are at the low level so that the output signals of the sense amplifier drivers SAD1 . . . SADN, the word drivers WD1 . . . WDn and the bit line balance and precharge circuit drivers BBD1 . . . BBDn are at the low level. Therefore the sense amplifier circuits SA1 . . . SAn and the row decoders RD1 . . . RDn are deactivated and do not amplify voltages of any bit line pairs BL11a, BL11b or select any word lines WL11, respectively, whereas the bit line balance and precharge circuits BB1 . . . BBn are activated to balance and precharge the bit line pairs BL11a, BL11b. Then the block address signal AddB1 is supplied to the block selector BS which decodes the address signal AddB1 and selectively turns one of the block selection signals SL1 . . . SLn to the high level. FIG. 12 shows a case where the block selection signal SL1 turns to the high level, selecting the memory cell array block CAB1. Therefore the x-predecoder PD1 is activated according to the block selection signal SL1 to receive, and predecodes the row address signal AddR1 and outputs the predecoded address signal PD1out to the row decoder RD1. This predecode operation takes the predecode time Tpd shown in FIG. 12. Concurrently the sense amplifier driver SAD1, the word driver WD1 and the bit line balance and precharge circuit driver BBD1 turn their output signals SAD1out, WD1out, BBd1out to the high level according to the signal SL1 as shown in FIG. 12 so that the bit line balance and precharge circuit BB1 is deactivated to stop the balance and precharge operation and the row decoder RD1 is activated and becomes capable to decode the predecoded address signal PD1out and drive the selected word line WL11. The sense amplifier circuit SA1 is also activated and, at the certain timing after the word line WL11 is driven to the high level and the memory cells MC111 are connected to the bit line pairs BL11a, BL11b, starts to amplify the voltages on the bit line pairs BL11a, BL11b. In the nonselected block areas Bn, the memory cell array blocks CABn are maintained in the balanced and precharged state and the x-predecoders PDn are also deactivated. Therefore, the current consumption owing to the charging and discharging operations in the nonselected memory cell array blocks CABn is prevented and the current consumption in the x-predecoder PDn owing to predecode operations thereof is also prevented.
Meanwhile, when the column address strobe signal CAS goes to the low level, the timing controller TC outputs the address latch signal AL21 and the address enable signal AE21 the address buffer AB2 which outputs the column address signal AddC1 to the column decoders CD1 . . . CDn. In this case, however, only the column decoder CL1 is activated according to the signal SL1 so that the column decoder CD1 output the column selection signal to the column selector CS1 which selectively connect the bit line pair BL11a, BL11b and the amplifier associated therewith to the data line DL1a. Consequently, the data in the selected memory cell MC111 of the memory cell array block CAB1 is output and transferred to the read amplifier RA9 via the data line Db1a.
According to the transition of the signal CAS to the high level, the address buffer AB2 stops outputting the column address signal AddC1 so that the column selector CS1 also stops connecting the bit line pair to the data line DL1a and the data transfer operation on the data line DL1a is completed at the time t21 as shown in FIG. 12. That is, the access operation to the memory cell array block CAB1 is substantially completed at this time t21.
After that the signal RAS goes to the high level at the time t31 and the address buffer AB1 stops outputting the address signal AddB1 to the block selector BS which, therefore, turns the block selection signal SL1 to the low level. Therefore, the sense amplifier driver SAD1, the word driver WD1, the x-predecoder PD1 and the bit line balance and precharge circuit driver BBD1 output the low level signals and the voltage of the selected word line WL11 is decreased to the low level at the time t41 as shwon in FIG. 12. Then all of the memory cell array blocks CAB1 . . . CABn enter the balanced and precharged state wherein any word lines WL11 or bit line pairs BL11a, BL11b are not selected. After time t41, the RAM device is in an initial state again and ready to perform the next operations at time t51 shown in FIG. 12.
The write operation is performed in almost the same manner as the read operation. When the input buffer IB9 is activated according to a write enable signal WE, the write data is transferred via the write amplifier WA9 and the data line DL1a to the selected memory cell MC111 according to the address signals AddR, AddB, AddC.
During a refresh mode operation on the memory cell array block CAB1, the address buffer AB1 outputs the address signal AddB1 which indicates the memory cell array block CAB1 according to a control signal from the refresh counter RC. Then the address buffer AB1 continuously outputs the address signals AddR1 indicating the all or particular row addresses of the memory cell array CAB1 which needs refresh operation according to the control signal from the refresh counter RC. Therefore, in the memory cell array block CAB1, the word lines WL11 corresponding to the address signals AddB1 are activated and the memory cells MC111 associated therewith are refreshed by the sense amplifier circuit SA1, that is, the memory cells MC111 are fully charged or discharged according to the stored data thereof. The refresh operations on any other memory cell array blocks CABn are performed in a same manner as above.
The page mode operation, in which a word line is activated and a number of memory cells associated with the word line are accessed to perform read or write operations continuously in order to increase the access speed, is also achieved in almost the same manner as the above mentioned read write operations. In the page mode operation, the signal CAS turns to the low level several times so as to input or output the data during an single time period wherein the signal RAS continues to be at the low level, that is, between the time t11 to t31 in FIG. 10.
However, as apparent from the above explanation, in this prior art device, since the selected word line WL11 is at high level only during a certain time period corresponding to the signal RAS, it is neccessary to maintain the signal RAS in the low level until the access operation, that is a read or write operation, is substantially completed at the time t21 in order to avoid any operation errors which may occur when the word line voltage is decreased too early. In other words, the operations for activating the selected word line and deactivating it are respectively needed just before and just after the column access operation which is indicated by the signal CAS. Therefore, in this device, the comparatively long interval, which corresponds to the period between the time t21 and t51, is needed and the total access operation time, which is determined by the time t11 and t61, becomes quite long, even when the different memory cell array blocks are selected sequentially.
Moreover, even when this prior art device performs page mode operations, since the page mode operations to be performed subsequently must have a long interval there between as mentioned above, the total operation speed is not effectively improved. In particular, in the device having a plurality of memory cell array blocks, each word line is formed in short length so as to reduce the current consumption as mentioned above, so that the number of memory cells associated with a common word line is comparatively small, that is, the number of data bits which can be dealt with in a single page mode operation is highly restricted. Therefore, the page mode operations must have many long intervals, making total operation time of the device long.
Furthermore, since it is necessary to maintain the signal RAS in the low level all through the access operation, when one memory cell array block CAB1 is activated to perform a page mode operation, which takes a comparatively long time, any other memory cell array blocks CABn cannot be accessed even though the word drivers WDn, the row decoders RDn and the x-predecoders PDn thereof are not used in the operation on the activated memory cell array block CAB1, but are available to perform the next operations. This device is, similarly, not available to perform any read andr write operations when one memory cell array block is in a self refresh operation mode. Accordingly, the total operation speed of this prior art device is considerably low and, moreover, this prior art device is restricted in its use and cannot be available for flexible uses, such as, the frame buffer application, in which the data of one page or one word line of a memory cell array block are read out and transferred continuously into a certain page of a video RAM device which corresponds to a certain frame of video picture and, at the same time, the data corresponding to the next page (frame) are prepared or generated in any other part of the video system and transported into a certain page of another memory cell array block so as to increase the operation speed of the memory device and the whole of the video system.